I made some updates to the NetSID project. You can download the full ISE project from https://baker76.com/download/fpga/netsid.zip

There are now two ISE project files NetSID_pipistrello.xise and NetSID_papilio.xise which have the appropriate ucf and clock files. These support the Pipistrello and Papilio FPGA development boards respectively.

Here is a list of the main changes:

1. It now has the latest SID vhdl (with filters) from https://github.com/MEGA65/mega65-core/tree/master/src/vhdl
   • sid_6581.vhd
   • sid_coeffs.vhd
   • sid_components.vhd
   • sid_filters.vhd
   • sid_voice.vhd
2. Added an audio mixer from https://github.com/GadgetFactory/ZPUino-HDL/tree/master/zpu/hdl/zpuino/contrib
   • simple_sigmadelta.vhd
   • zpuino_audiomixer.vhd
3. Added the latest async.v from https://www.fpga4fun.com/files/async.zip which contains the latest versions of async_transmitter and async_receiver
4. Added 2SID and 3SID support
   • There is a demo song included called Earmind_3SID.sid
   • Reading the documentation for the Network SID Device Protocol (https://sourceforge.net/p/jsidplay2/code/HEAD/tree/trunk/jsidplay2/src/main/asciidoc/netsiddev.adoc) the TRY_WRITE command has a 3rd byte which is an 8-bit SID register number from 0x00 to 0x1f. It doesn't mention it but I found by looking at the source that bits 5 to 6 store the SID number when the song supports multiple SIDs.
   • If you run the !play_csid.bat batch file it will run the csid SID player which supports 3SID format so you can compare the results with the FPGA version.
5. Output from "server_v2_HybridSID - handshake.py" now shows the sid_number variable so you know which SID the data is outputting to

Eg.

using COM15
listening on port 6581
connected
    sid count: 3
[0] model: 0
[0] position: 206
[1] model: 0
[1] position: 50
[2] model: 0
[2] position: 206
[0] resampling method: low quality
[0] clock source speed: PAL
[0] clock source speed: PAL
[0] clock source speed: PAL
    sid count: 3
[0] model: 0
[0] position: 206
[1] model: 0
[1] position: 50
[2] model: 0
[2] position: 206
[0] resampling method: low quality
[0] clock source speed: PAL
    FPGA requested pause, buffer full...
[2] 39346 Bytes/s, block size: 288
    FPGA requested pause, buffer full...
[0] 30406 Bytes/s, block size: 316
    FPGA requested pause, buffer full...
[2] 29653 Bytes/s, block size: 332
    FPGA requested pause, buffer full...
[2] 30620 Bytes/s, block size: 300
    FPGA requested pause, buffer full...
[0] 30347 Bytes/s, block size: 316
    FPGA requested pause, buffer full...
[1] 30633 Bytes/s, block size: 316
    FPGA requested pause, buffer full...
[2] 29623 Bytes/s, block size: 332
    FPGA requested pause, buffer full...

UPDATE: This project is now hosted on GitHub here

I'm playing around with my iCEBreaker FPGA today. Got output to an RGB Matrix using the LED panel driver Pmod.

I have a project in which I want to create a console in FPGA and was disappointed to find the Papillo project was pretty much dead and did not support the Xliinx 7 series. I found the Bonfire RISC-V (RV32IM) processor and decided this would be a great replacement for the ZPUino.

I recently purchased an Arty A7-35T board so I can run the Bonfire processor. I plugged in a Micro SD and USBUART Pmod. The Micro SD slot is for storing and running Lua applications and the USBUART Pmod is for debugging (more on that in another post).

I successfully flashed the bonfire_arty_rev_v1.2.0_elua_0.9.1_193-gb2bf8f8.mcs image.

The first issue I came across is the Configuration Memory Device is different on my board. Mine has a Spansion s25fl128sxxxxxx0-spi-x1_x2_x4 not a Micron mt25ql128-spi-x1_x2_x4.

The second issue I had was using minicom. I could not get any response from the board until I did the following:

1. Press CTRL-A Z
2. Select "o" (cOnfigure Minicom)
3. Select "Serial port setup"
4. Use F and G to set:
   • F - Hardware Flow Control : No
   • G - Software Flow Control : Yes
5. Press ESC until you are back to the main prompt

So now I have successfully connected to my Arty running Bonfire processor! 😄